Physical Design for VLSI Circuits

VLSI Design flow, Physical Design Cycle, VLSI Design Styles, Common EDA Terminology. Partitioning – Problem formulation, Classification of Partitioning algorithms, Kernighan-Lin Algorithm, Simulated Annealing, Fiduccia-Mattheyses (FM) Algorithm.

Floor Planning – Problem formulation, Classification of floor planning algorithms, constraint-based floor planning, Rectangular Dualization, Pin Assignment – Problem formulation, Classification of pin assignment algorithms, General and channel Pin assignments.

standard cell placement, timing-driven placement, Classification of placement algorithms, Partitioning based placement algorithms. Power planning and IR drop considerations

Clock Tree Synthesis (CTS) and Routing Clock distribution challenges: skew, latency, and insertion delay, CTS methodologies: H-tree, X-tree, and balanced clock trees, Clock gating. Global routing and detailed routing techniques, Routing constraints: DRC, wire load models, parasitic extraction

Timing and Power Analysis Static Timing Analysis (STA): setup and hold analysis, Timing closure challenges and optimization techniques Power analysis: dynamic, leakage, IR drop, and power grid design