Physical Design for VLSI Circuits Lab

List of Experiments / Activities

1. LAB 0L:0T:2P 1 Credits
2. SUGGESTIVE LIST OF EXPERIMENTS:
3. 1Perform RTL synthesis to generate a gate-level netlist from Verilog or VHDL code.
4. 2Make Floorplan of a Digital Design Block
5. 3Carry out standard cell and macro placement to optimize area and performance.
6. 4Power Planning: Creation of Power Rings and Straps
7. 5Design and analyze a clock tree structure to minimize skew and meet timing constraints.
8. 6Perform global and detailed routing to complete interconnections between placed cells.
9. 7Perform static timing analysis to verify setup and hold timing violations.
10. 8Parasitic Extraction and RC Delay Estimation
11. 9Conduct Design Rule Check (DRC) and Layout Versus Schematic (LVS) Verification.
12. 10Generate the final GDSII file for fabrication-ready layout submission.
13. Content beyond the Course: Experiments related to RTL synthesis, floorplanning, standard cell placement, power planning, clock tree synthesis (CTS), global and detailed routing, static timing analysis (STA), parasitic extraction, RC delay estimation, Design Rule Check (DRC), Layout Versus Schematic (LVS) verification, and GDSII generation, as covered in this suggestive list, can be implemented and verified using “Siemens EDA (Calibre)/ Cadence/ Synopsys or similar relevant software tools”.